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1.使用"加减计数"指令，可以递增和递减输出CV的计数器值。
2. 当输入CU的信号状态从低电平（“0”）变为高电平（“1”）时（即信号上升沿触发），当前计数器值将加1并存储在输出CV中。当输入CD的信号状态从低电平（“0”）变为高电平（“1”）时（即信号上升沿触发），输出CV的计数器值将减1。如果在一个程序周期内，同时出现CU和CD的信号上升沿，输出CV的当前计数器值将保持不变。
3. 计数器值可以不断递增，直到达到输出CV所指定的数据类型的上限。一旦达到上限，即使出现信号上升沿，计数器值也不再递增。达到指定数据类型的下限后，计数器值将不再递减。
4. 当输入LD的信号状态变为高电平（“1”）时，输出CV的计数器值将设置为参数PV的值。只要输入LD的信号状态仍为高电平（“1”），输入CU和CD的信号状态就不会影响该指令的执行。
5. 当输入R的信号状态变为高电平（“1”）时，将计数器值重置为0。只要输入R的信号状态仍为高电平（“1”），输入CU、CD和LD的信号状态的变化将不会影响"加减计数"指令。
6. 如果当前计数器值大于或等于参数PV的值，则将输出QU的信号状态置为高电平（“1”）。在其他情况下，输出QU的信号状态为低电平。
7. 如果当前计数器值小于或等于0，则将输出QD的信号状态置为高电平（“1”）。在其他情况下，输出QD的信号状态为低电平（“0”）。
1. Use the "add subtract count" command to increase and decrease the counter value of the output CV.
When the signal state of the input CU changes from low level ("0") to high level ("1") (i.e. the rising edge of the signal is triggered), the current counter value will be incremented by 1 and stored in the output CV. When the signal state of the input CD changes from low level ("0") to high level ("1") (i.e. the rising edge of the signal is triggered), the counter value of the output CV will decrease by 1. If both CU and CD signal rising edges occur within one program cycle, the current counter value of the output CV will remain unchanged.
3. The counter value can continuously increase until it reaches the upper limit of the data type specified by the output CV. Once the upper limit is reached, even if there is a rising edge of the signal, the counter value will no longer increase. After reaching the lower limit of the specified data type, the counter value will no longer decrease.
When the signal state of the input LD changes to high level ("1"), the counter value of the output CV will be set to the value of the parameter PV. As long as the signal status of the input LD remains high ("1"), the signal status of the input CU and CD will not affect the execution of the instruction.
When the signal state of input R changes to high level ("1"), reset the counter value to 0. As long as the signal state of the input R remains high ("1"), changes in the signal state of the input CU, CD, and LD will not affect the "add subtract count" instruction.
If the current counter value is greater than or equal to the value of parameter PV, set the signal state of output QU to high level ("1"). In other cases, the signal state of the output QU is low.
If the current counter value is less than or equal to 0, set the signal status of the output QD to high level ("1"). In other cases, the signal state of the output QD is low ("0").
